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general description the max8649/max8649a high-efficiency dc-to-dc step- down switching regulators deliver up to 1.8a of output cur- rent. the device operates from a 2.5v to 5.5v input voltage range, making it future proof for next-generation battery technologies. the output voltage is i 2 c program- mable from 0.75v to 1.38v. remote sense ensures pre- cise dc regulation at the load. total output error is less than 2% over load, line, and temperature. the ics operate at a 3.25mhz fixed frequency. the high operating frequency minimizes the size of external com- ponents. the switching frequency of the converter can be synchronized to the master clock of the application. when synchronizing to an external clock, the ics measure the frequency of the external clock to ensure that the clock is stable before changing the switching frequency to the external clock frequency. an on-board dac allows adjustment of the output volt- age in 10mv steps. the output voltage can be pro- grammed directly through the i 2 c interface, or by preloading a set of on-board registers and using the two vid logic signals to select the appropriate register. other features include internal soft-start control circuitry to reduce inrush current, output overvoltage, overcur- rent, and overtemperature protection. the ics feature different i 2 c addresses so that devices may be used in a system. for a 2.5a version of this device, refer to the max8952 data sheet. applications cell phones and smartphones pdas and mp3 players features 1.8a guaranteed output current i 2 c programmable v out (750mv to 1.38v in 10mv steps) operates from 2.5v to 5.5v input supply on-chip fet and synchronous rectifier fixed 3.25mhz pwm switching frequency synchronizes to 13mhz, 19.2mhz, or 26mhz system clock when available small 1.0 h inductor initial accuracy 0.5% at 1.25v output 2% output accuracy over load, line, and temperature power-save mode increases light load efficiency overvoltage and overcurrent protection thermal shutdown protection 400khz i 2 c interface < 1 a shutdown current 16-bump, 2mm x 2mm wlp package max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp ________________________________________________________________ maxim integrated products 1 19-4504; rev 4; 6/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available ordering information part pin-package i 2 c address (write/read) max8649 ewe+t 16 wlp (0.5mm pitch) 0xc0/0xc1 max8649a ewe+t 16 wlp (0.5mm pitch) 0xc4/0xc5 + denotes a lead(pb)-free/rohs-compliant package. note: all devices operate over the -40? to +85? temperature range. bump configuration + wlp 0.5mm pitch b2 b4 c4 b3 b1 a4 a3 a2 a1 d4 c1 d1 c3 c2 d3 d2 in1 agnd in2 en lx lx sns- vid0 pgnd pgnd v dd sda scl sync vid1 sns+ top view (bumps on bottom) typical operating circuit 2.5v to 5.5v v out (0.75v to 1.38v) lx in2 v dd scl 1.8v to 3.6v 2.5v to 5.5v 11 0.1 f 10 f 0.1 f 10 f 0.1 f sda in1 fsync pgnd sns+ sns- en vid0 vid1 agnd max8649 max8649a 1 h cpu 0.1 f 2.2 f
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in1 = v in2 = 3.6v, v agnd = v pgnd = 0v, v dd = 1.8v, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in1, in2 to agnd ..................................................-0.3v to +6.0v v dd to agnd.........................................................-0.3v to +4.0v lx, sns+, vid0, vid1, en to agnd..........-0.3v to (v in1 + 0.3v) scl, sda, sync to agnd.........................-0.3v to (v dd + 0.3v) pgnd, sns- to agnd...........................................-0.3v to +0.3v rms lx current ..............................................................1800ma continuous power dissipation (t a = +70?) 16-bump wlp 0.5mm pitch (derate 13mw/? above +70?) ............................1040mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? soldering temperature (reflow) .......................................+260? parameter conditions min typ max units in1, in2 operating range 2.5 5.5 v v dd operating range 1.8 3.6 v v dd undervoltage lockout (uvlo) threshold v dd falling 0.54 0.865 1.35 v v dd uvlo hysteresis 50 mv in_ undervoltage lockout (uvlo) threshold v in falling 2.10 2.15 2.20 v in_ uvlo hysteresis 70 mv t a = +25? 0.01 1 v dd shutdown supply current v in1 = v in2 = 5.5v, en = v dd = agnd t a = +85? 0.01 ? t a = +25? 0.25 1 in1, in2 shutdown supply current v in1 = v in2 = 5.5v, en = v dd = agnd t a = +85? 0.25 ? t a = +25? 0.35 1 in1, in2 standby supply current v in1 = v in2 = 5.5v, scl = sda = v dd , en = agnd, i 2 c ready t a = +85? 0.35 ? t a = +25? 0.02 1 v dd standby supply current v in1 = v in2 = v dd = 3.6v, scl = sda = v dd , en = agnd, i 2 c ready t a = +85? 0.02 ? logic interface en, vid0, vid1 1.4 logic input high voltage (v ih ) v in1 = v in2 = 2.5v to 5.5v, v dd = 1.8v to 3.6v sync, scl, sda 0.7 x v d d v en, vid0, vid1 0.4 logic input low voltage (v il ) v in1 = v in2 = 2.5v to 5.5v, v dd = 1.8v to 3.6v sync, scl, sda 0.3 x v d d v t a = +25? -1 0.01 +1 sda, scl, sync logic input current v il = 0v or v ih = 3.6v, en = agnd t a = +85? 0.01 ? note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . wlp junction to ambient thermal resistance ( ja )............76?/w package thermal characteristics (note 1)
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp _______________________________________________________________________________________ 3 parameter conditions min typ max units vid0, vid1, en logic input pulldown resistor controlled by i 2 c command: vid0_pd = 1 vid1_pd = 1 en_pd = 1 200 320 450 k i 2 c interface sda output low voltage i sda = 3ma 0.03 0.4 v i 2 c clock frequency 400 khz bus-free time between start and stop t buf 1.3 ? hold time repeated start condition t hd_sta 0.6 0.1 ? scl low period t low 1.3 0.2 ? scl high period t high 0.6 0.2 ? setup time repeated start condition t su_sta 0.6 0.1 ? sda hold time t hd_dat 0 -0.01 ? sda setup time t su_dat 0.1 0.05 ? setup time for stop condition t su_sto 0.6 0.1 ? step-down dc-dc regulator operation_mode_ = 0, v out = 1.27v, no switching 54 70 ? in1 + in2 supply current operation_mode_ = 1, v out = 1.27v, f sw = 3.25mhz 9 ma minimum output capacitance required for stability v out = 0.75v to 1.38v, i out = 0 to 1.8a 10 ? out voltage range 10mv steps 0.750 1.380 v output overvoltage protection rising, 50mv hysteresis (typ) 1.65 1.8 1.9 v electrical characteristics (continued) (v in1 = v in2 = 3.6v, v agnd = v pgnd = 0v, v dd = 1.8v, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2)
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp 4 _______________________________________________________________________________________ electrical characteristics (continued) (v in1 = v in2 = 3.6v, v agnd = v pgnd = 0v, v dd = 1.8v, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter conditions min typ max units no load, v in_ = 2.5v to 5.5v, v out = 1.27v operation_mode_ = 1 -0.5 +0.5 i out = no load, v in_ = 2.5v to 5.5v, v out = 0.75v, operation_mode_ = 1 -1.0 +1.0 out voltage accuracy i out = no load, v in_ = 2.5v to 5.5v, v out = 1.38v, operation_mode_ = 1 -0.5 +0.5 % load regulation r l is the resistance from lx to sns+ (output) r l /25 v/a ramp[2:0] = 000 32.50 ramp[2:0] = 001 16.25 ramp[2:0] = 010 8.125 ramp[2:0] = 011 4.063 ramp[2:0] = 100 2.031 ramp[2:0] = 101 1.016 ramp[2:0] = 110 0.508 ramp timer ramp[2:0] = 111 0.254 mv/? peak current limit (p-channel mosfet) pwm and hysteretic mode 2.3 2.8 3.2 a valley current limit (n-channel mosfet) hysteretic mode 1.8 2.4 3.0 a negative current limit (n-channel mosfet) pwm mode 2.0 2.5 3.0 a n-channel zero-crossing threshold 50 ma lx pfet on-resistance in2 to lx, i lx = -200ma 0.08 0.16 lx nfet on-resistance operation_mode = 0 lx to pgnd, i lx = 200ma 0.06 0.12 t a = +25? -1 0.03 +1 lx leakage v lx = 5.5v or 0v t a = +85? 0.05 ? internal oscillator, pwm 2.82 3.25 3.56 internal oscillator, power-save mode before entering pwm mode 2.43 3.25 4.06 13mhz option f sync /4 19.2mhz option f sync /6 operating frequency 26mhz option f sync /8 mhz
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp _______________________________________________________________________________________ 5 electrical characteristics (continued) (v in1 = v in2 = 3.6v, v agnd = v pgnd = 0v, v dd = 1.8v, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter conditions min typ max units minimum duty cycle forced pwm mode only, minimum duty cycle in (operation_mode_ = 1) = 0% 16 % maximum duty cycle 60 % minimum on- and off-time 30 40 50 ns out discharge resistance during shutdown or uvlo, from sns+ to pgnd 650 sns+, sns- input impedance v out = 0.75v (out_modex [5:0] = 0b000000) 400 600 850 k time delay from pwm to power-save mode time required for error amplifier to stabilize before switching mode 70 ? time delay from power-save mode to pwm time required for error amplifier to stabilize before switching mode 140 ? synchronization (sync) sync = 00 default 18.9 26.0 38.0 sync = 1x default 14.2 19.2 28.5 sync capture range sync = 01 default 9.5 13.0 19.0 mhz sync pulse width 13 ns protection circuits thermal-shutdown hysteresis 20 ? thermal shutdown +160 ? note 2: all devices are 100% production tested at t a = +25?. limits over the operating temperature range are guaranteed by design.
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp 6 _______________________________________________________________________________________ efficiency vs. load current (0.9v output, sync off) max8649/49a toc01 load current (a) efficiency (%) 1 0.1 0.01 0.001 10 20 30 40 50 60 70 80 90 100 0 0.0001 10 power save forced pwm v in = 3.2v 3.6v 4.2v efficiency vs. load current (1.1v output, sync off) max8649/49a toc02 load current (a) efficiency (%) 1 0.1 0.01 0.001 10 20 30 40 50 60 70 80 90 100 0 0.0001 10 power save forced pwm v in = 3.2v 3.6v 4.2v efficiency vs. load current (1.3v output, sync off) max8649/49a toc03 load current (a) efficiency (%) 1 0.1 0.01 0.001 10 20 30 40 50 60 70 80 90 100 0 0.0001 10 power save forced pwm v in = 3.2v 3.6v 4.2v efficiency vs. load current (0.9v output, 26mhz sync) max8649/49a toc04 load current (a) efficiency (%) 1 0.1 0.01 0.001 10 20 30 40 50 60 70 80 90 100 0 0.0001 10 power save forced pwm v in = 3.2v 3.6v 4.2v efficiency vs. load current (1.1v output, 26mhz sync) max8649/49a toc05 load current (a) efficiency (%) 1 0.1 0.01 0.001 10 20 30 40 50 60 70 80 90 100 0 0.0001 10 power save forced pwm v in = 3.2v 3.6v 4.2v efficiency vs. load current (1.3v output, 26mhz sync) max8649/49a toc06 load current (a) efficiency (%) 1 0.1 0.01 0.001 10 20 30 40 50 60 70 80 90 100 0 0.0001 10 power save forced pwm v in = 3.2v 3.6v 4.2v switching frequency vs. load current max8649/49a toc07 load current (a) switching frequency (mhz) 1.5 1.2 0.9 0.6 0.3 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0 1.8 transition to pwm forced pwm power save v in = 3.6v v out = 1.3v 60 35 10 -15 -40 85 3.1 3.2 3.3 3.4 3.5 3.6 3.0 temperature ( c) switching frequency (mhz) max8649/49a toc08 switching frequency vs . temperature no sync 1.3v output, 500ma load no-load supply current vs. supply voltage (power save) supply voltage (v) supply current (ma) 4.5 3.5 0.1 0.2 0.3 0.4 0.5 0.6 0 2.5 5.5 max8649/49a toc09 26mhz sync no sync typical operating characteristics ( typical operating circuit , v in1 = v in2 = 3.6v, v agnd = v pgnd = 0v, v out = 1.1v, v dd = 1.8v, t a = +25?, unless otherwise noted.)
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp _______________________________________________________________________________________ 7 no-load supply current vs. supply voltage (forced pwm) max8649/49a toc10 supply voltage (v) supply current (ma) 4.5 3.5 2 4 6 8 10 12 14 16 18 20 0 2.5 5.5 no sync 26mhz sync 1.6 1.2 0.8 0.4 0 2.0 1.27 1.28 1.29 1.30 1.31 1.32 1.26 load current (a) output voltage (v) max8649/49a toc11 output voltage vs . load current v out = 1.3v t a = +25 n c t a = +85 n c t a = -40 n c power save output voltage vs. load current load current (a) output voltatge (v) 1.5 1.2 0.9 0.6 0.3 1.090 1.095 1.100 1.105 1.110 1.115 1.085 0 1.8 max8649/49a toc12 v out = 1.1v forced pwm power save output voltage vs. load current load current (a) output voltatge (v) 1.5 1.2 0.9 0.6 0.3 0.885 0.890 0.895 0.900 0.905 0.910 0.880 0 1.8 max8649/49a toc13 v out = 0.9v forced pwm power save light load switching waveforms max8649/49a toc14 2v/div 20mv/div 200ma/div v out v lx i l 2s/div 10ma load, v out = 1.3v medium load switching waveforms max8649/49a toc15 2v/div 20mv/div 500ma/div v out v lx i l 200ns/div 500ma load v out = 1.3v heavy load switching waveforms max8649/49a toc16 2v/div 20mv/div 1a/div v out v lx i l 200ns/div 1.8a load v out = 1.3v typical operating characteristics (continued) ( typical operating circuit , v in1 = v in2 = 3.6v, v agnd = v pgnd = 0v, v out = 1.1v, v dd = 1.8v, t a = +25?, unless otherwise noted.)
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp 8 _______________________________________________________________________________________ light load startup waveforms max8649/49a toc17 100ma/div 500ma/div 1v/div 5v/div v out i in i l v en 200s/div 10 i load heavy load startup waveforms max8649/49a toc18 200ma/div 500ma/div 1v/div 5v/div v out i in i l v en 200s/div 1 i load prebias startup waveforms (forced pwm) max8649/49a toc19 500mv/div 1a/div 5v/div v out i l v en 200s/div output prebiased to 1.3v startup to 1.1v line transient response (4.2v to 3.2v to 4.2v) sync off max8649/49a toc20 1v/div 20mv/div 200ma/div v out i l 20s/div 300ma load v in line transient response (4.2v to 3.2v to 4.2v) 26mhz sync max8649/49a toc21 1v/div 20mv/div 200ma/div v out i l 20s/div 300ma load v in load transient response (1ma to 1a) max8649/49a toc22 50mv/div 500ma/div 1a/div v out i out i l 40s/div typical operating characteristics (continued) ( typical operating circuit , v in1 = v in2 = 3.6v, v agnd = v pgnd = 0v, v out = 1.1v, v dd = 1.8v, t a = +25?, unless otherwise noted.)
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp _______________________________________________________________________________________ 9 load transient response (1a to 1ma) max8649/49a toc23 50mv/div 500ma/div 1a/div v out i out i l 40s/div load transient response (5ma to 1.8a) max8649/49a toc24 50mv/div 1a/div 1a/div v out i out i l 40s/div load transient response (1.8a to 5ma) max8649/49a toc25 100mv/div 1a/div 1a/div v out i out i l 20s/div synchronization response (26mhz sync) max8649/49a toc26 200ma/div 2v/div 20mv/div 2v/div v sync v lx i l v out 1s/div forced pwm, no load output voltage change response max8649/49a toc27 200ma/div 500mv/div 2v/div v vid0 i l v out 40s/div 10 i load, power save 32mv/s ramp 0.9v 0.9v 1.3v typical operating characteristics (continued) ( typical operating circuit , v in1 = v in2 = 3.6v, v agnd = v pgnd = 0v, v out = 1.1v, v dd = 1.8v, t a = +25?, unless otherwise noted.)
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp 10 ______________________________________________________________________________________ bump description pin name function a1 in1 anal og s up p l y v ol tag e inp ut. the i np ut vol tag e r ang e i s 2.5v to 5.5v . place an 11 resistor between in1 and the input supply. byp ass in 1 to anal og g r ound w i th a 0.1f cer am i c cap aci tor as cl ose as p ossi b l e to the ic . c onnect in 1 and in 2 to the sam e p ow er sour ce. a2 agnd analog ground. connect agnd to the pcb ground plane. a3 vid1 voltage id control input. the logic states of vid0 and vid1 select the register that sets the output voltage. a4 in2 power-supply voltage input. the input voltage range is from 2.5v to 5.5v. in2 powers the internal p-channel and n-channel mosfets. bypass in2 to pgnd with 10? and 0.1? ceramic capacitors as close as possible to the ic. connect in1 and in2 to the same power source. b1 sns+ output voltage remote sense, positive input. connect sns+ directly to the output at the load. b2 en logic enable input. drive en high to enable the dc-dc step-down regulator, or low to place in shutdown mode. in shutdown mode, this logic input has an internal pulldown resistor to agnd. b3, b4 lx inductor connection. lx is connected to the drains of the internal p-channel and n-channel mosfets. lx is high impedance during shutdown. c1 sns- output voltage sense, negative input. connect to a quiet ground directly at the ic. c2 vid0 voltage id control input. the logic states of vid0 and vid1 select the register that sets the output voltage. c3, c4 pgnd power ground. connect both pgnd bumps to the pcb ground plane. d1 v dd logic input supply voltage. connect v dd to the logic supply driving sda, scl, and sync. bypass v dd to agnd with a 0.1? ceramic capacitor. when v dd drops below the uvlo threshold, the i 2 c registers are reset, but the en control is still active in this mode. d2 sda i 2 c d ata inp ut. d ata i s r ead on the r i si ng ed g e of s c l and d ata i s cl ocked out on the fal l i ng ed g e of s c l. d3 scl i 2 c clock input d4 sync e xter nal c l ock s ynchr oni zati on inp ut. c onnect s y n c to a 13m h z, 19.2m h z, or 26m h z system cl ock. the d c - d c r eg ul ator can b e for ced to synchr oni ze to thi s exter nal cl ock d ep end i ng on i 2 c setti ng . s ee tab l e 8. s y n c d oes not have an i nter nal p ul l d ow n. c onnect s y n c to ag n d i f not used .
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp ______________________________________________________________________________________ 11 i 2 c interface voltage control, v ref , bias, etc. pwm logic clock gen osc v dac sns- sns+ pgnd lx in2 agnd vid1 vid0 en in1 sda scl v dd sync max8649 max8649a figure 1. block diagram detailed description the max8649/max8649a high-efficiency, 3.25mhz step-down switching regulator delivers up to 1.8a of output current. the device operates from a 2.5v to 5.5v input voltage range, and the output voltage is i 2 c pro- grammable from 0.75v to 1.38v in 10mv increments. remote sense ensures precise dc regulation at the load. total output error is less than 2% over load, line, and temperature. the ics feature different i 2 c address- es so that multiple devices may be used in a system (see the ordering information section.) dynamic voltage scaling the output voltage is dynamically adjusted by use of the vid0 and vid1 logic inputs, allowing selection between four predefined operation modes/voltage configurations. for each of the different output modes, the following parameters are programmable: output voltage from 0.75v to 1.38v in 10mv steps mode of operation: forced pwm or power save enable/disable of synchronization of switching frequency to external clock source the relation between the vid0/vid1 and operation mode is given by table 1. the vid_ inputs have internal pulldown resistors. these pulldown resistors can be disabled through the control register after the ics are enabled, achieving lowest possible quiescent current. when en is low, the con- trol register is reset to default, enabling the pulldown resistors (see table 7). vid1 vid0 mode i 2 c register default swithcing mode default syn c h r o n iz a tio n default output voltage (v) 0 0 mode0 table 3 forced pwm off 1.27 0 1 mode1 table 4 power save off 1.05 1 0 mode2 table 5 forced pwm off 1.23 1 1 mode3 table 6 forced pwm off 1.05 table 1. vid0 and vid1 configuration
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp 12 ______________________________________________________________________________________ a in a: power connected to in1 and in2. b: en logic input pulled high, output voltage is set to condition defined by the default value of the i 2 c register for mode0 (see table 1). c: output voltage is set to condition defined by the i 2 c register for mode1. d: output voltage is set to condition defined by the default value of i 2 c register for mode3. e: v dd pulled high, enabling i 2 c interface. out en vid1 vid0 v dd bcde 1.27v 1.23v 1.05v figure 2. power-up sequence enable the dc-dc step-down regulators are enabled/disabled using the en logic input. the en input is able to handle input voltages up to v in1 , ensuring that the en logic input can be controlled by a wide variety of signals/supplies. the en input has an internal pulldown resistor that ensures en is discharged during off conditions. this pulldown resistor can be disabled through the control register (see table 7) once the ics are enabled, achieving lowest possible quiescent current. when en is low, the control register is reset to default, enabling the pulldown resistors on en, vid0, and vid1. see figures 2 and 3 for detailed information on power-up and power-down sequencing and opera- tion mode changes. dc-dc regulator operating modes the ics operate in one of four modes determined by the state of the vid_ inputs (see table 1). at power-up, the ics are default set to operate in power-save opera- tion for mode1 and forced-pwm mode for mode0, mode2, and mode3. for each of the operation modes, mode0 to mode3, the dc-dc step-down regulators can be set to operate in either power-save mode or forced-pwm mode. this is done by writing to the mode_ registers (see table 3 to table 6). the mode of operation can be changed at any time. in power-save mode, the pwm switching frequency depends on the load current. for medium to high load condition, the ics operate in fixed-frequency pwm mode. for light load conditions, the ics operate in hys- teretic mode. the proprietary hysteretic pwm control scheme ensures high efficiency, fast switching, and fast transient response. this control scheme is simple: when the output voltage is below the regulation thresh- old, the error comparator begins a switching cycle by turning on the high-side switch. this switch remains on until the minimum on-time expires and the output volt- age is above the regulation threshold plus hysteresis or the inductor current is above the current-limit threshold. once off, the high-side switch remains off until the minimum off-time expires and the output volt- age falls again below the regulation threshold. during the off period, the low-side synchronous rectifier turns on and remains on until either the high-side switch turns on again or the inductor current approaches zero. the internal synchronous rectifier eliminates the need for an external schottky diode.
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp ______________________________________________________________________________________ 13 a: v dd pulled low, i 2 c registers reset to default values (see table 1) and the output voltage changes to the default value. b: en logic input pulled low, step-down regulator enters shutdown mode. in out en v dd ab figure 3a. shutdown by pulling v dd low before en a: en logic input pulled low, step-down regulator enters i 2 c ready mode, output disabled. b: v dd pulled low, i 2 c registers reset to default values (see table 1). in out en v dd ab figure 3b. shutdown by pulling en low before v dd a: in1 drops below uvlo, ic enters shutdown mode, i 2 c registers reset to default values (see table 1). in1 out en v dd a figure 3c. shutdown due to in1 undervoltage lockout
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp 14 ______________________________________________________________________________________ the transition between pwm and hysteretic operation is based on the number of consecutive zero-crossing cycles. when more than 16 consecutive zero-crossing cycles are detected, the dc-dc step-down converter enables the bias for hysteretic operation. once correct- ly biased and the number of consecutive zero-crossing cycles exceeds 24, the dc-dc step-down converter begins hysteretic operation. during hysteretic operation, there is a silent dc offset due to the use of valley regulation. see figure 4. when operating in power-save mode and the load cur- rent is increased so that the number of consecutive zero-crossing cycles is less than 16, the pwm mode is biased. once fully biased and the number of zero- crossing cycles drops below 8, the dc-dc converter then begins pwm operation. since there is a delay between the increase in load current and the dc-dc converter starting pwm, the converter supports full current on the output during hysteretic operation. see figure 5 for a detailed state diagram. power-save operation offers improved efficiency at light loads by changing to hysteretic mode, reducing the switching frequency depending on the load condition. with moderate to heavy loading, the regulator switches at a fixed switching frequency as it does in forced-pwm mode. in power-save mode, the transition from hys- teretic mode to fixed-frequency switching occurs at the load current specified in the following equation: in forced-pwm mode, the regulator operates with a constant (3.25mhz or synchronized to external clock source) switching frequency regardless of output load. forced-pwm mode is ideal for low-noise systems because switching harmonics occur at multiples of the constant switching frequency and are easily filtered. however, light-load power consumption in forced-pwm mode is higher than that of power-save mode. i vv l v vf out in out out in osc = ? 2 pwm mode pwm mode with power-save mode biased power-save mode power-save mode with pwm biased pwm not ready power save not ready more than 24 consecutive zero-crossing cycles and power-save mode ready less than 8 consecutive zero-crossing cycles and pwm mode ready less than 16 consecutive zero-crossing cycles more than 24 consecutive zero-crossing cycles less than 8 consecutive zero-crossing cycles more than 16 consecutive zero-crossing cycles figure 5. mode change for dc-dc step-down converter output ripple regulation threshold figure 4. output regulation in hysteretic operation
max8649 soft-start the ics include internal soft-start circuitry that eliminates inrush current at startup, reducing transients on the input source (see the typical operating charac- teristics ). soft-start is particularly useful for high-imped- ance input sources, such as li+ and alkaline cells. when enabling the ics into a prebiased output, the ics perform a complete soft-start cycle. synchronous rectification an internal n-channel synchronous rectifier eliminates the need for an external schottky diode and improves efficiency. the synchronous rectifier turns on during the second half of each switching cycle (off-time). during this time, the voltage across the inductor is reversed, and the inductor current ramps down. in pwm mode, the synchronous rectifier turns off at the end of the switching cycle. in power-save mode, the synchronous rectifier turns off when the inductor current falls below 50ma (typ) or at the end of the switching cycle, whichever occurs first. ramp-rate control the output voltage has an actively controlled variable ramp rate, set with the i 2 c interface (see figures 6, 7, and 8). the value set in the ramp register controls the output voltage ramp rate. the ramp_down bit con- trols the active ramp-down behavior in power-save mode. when the regulator is set for power-save mode and the ramp_down bit is cleared, the ramp-down is not actively controlled, and the regulator output voltage ramps down at the rate determined by the output capacitance and the external load. small loads result in an output-voltage decay that is slower than that speci- fied by ramp; large loads result in an output-voltage decay that is no faster than that specified by ramp when the ramp_down bit is set in power-save mode, the zero-cross comparator is disabled during the ramp- down condition. active ramp-down functionality is inherent in forced-pwm operation. calculate the maximum and minimum values for the ramp rate as follows: where: f sw = 3.25mhz ?0% for pwm operation f sw = 3.25mhz ?5% for hysteretic operation f sync = frequency of external clock n = 4 for 13mhz, 6 for 19.2mhz, and 8 for 26mhz ramp_code = value of the ramp[2:0] register (see table 9) f f n sw sync = vmv t f t f out lsb clk max sw min clk min sw _ _ _ _ = = = 10 1 1 _ _max t v t t ramp min out lsb clk max ramp code ramp _ _ _ _ = 1 2 _ _ _ _ _ max out lsb clk min ramp code v t = 1 2 time output voltage delta v = 10mv v out v out ' 10mv/ramp rate figure 6. ramp-up function time output voltage delta v = 10mv v out ' v out 10mv/ramp rate figure 7. ramp-down function final output voltage mode change to higher vout mode change to lower vout figure 8. mode change before final value is reached 1.8a step-down regulator with remote sense in 2mm x 2mm wlp ______________________________________________________________________________________ 15
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp 16 ______________________________________________________________________________________ thermal-overload protection thermal-overload protection limits total power dissipa- tion in the ics. when internal thermal sensors detect a die temperature in excess of +160? (typ), the dc-dc step-down regulator is shut down, allowing the ic to cool. the dc-dc step-down regulator is turned on again after the junction cools by 20? (typ), resulting in a pulsed output during continuous thermal-overload conditions. during thermal overload, the i 2 c interface remains active and all register values are maintained. i 2 c interface an i 2 c-compatible, 2-wire serial interface controls the step-down converter output voltage, ramp rate, operat- ing mode, and synchronization. the serial bus consists of a bidirectional serial-data line (sda) and a serial- clock input (scl). the master initiates data transfer on the bus and generates scl to permit data transfer. i 2 c is an open-drain bus. sda and scl require pullup resistors (500 or greater). optional (24 ) in series with sda and scl protect the device inputs from high- voltage spikes on the bus lines. series resistors also minimize crosstalk and undershoot on bus signals. bit transfer one data bit is transferred during each scl clock cycle. the data on sda must remain stable during the high period of the scl clock pulse (see figure 9). changes in sda while scl is high are control signals (see the start and stop conditions section for more information). each transmit sequence is framed by a start (s) con- dition and a stop (p) condition. each data packet is 9 bits long; 8 bits of data followed by the acknowledge bit. the ics support data transfer rates with scl fre- quencies up to 400khz. start and stop conditions when the serial interface is inactive, sda and scl idle high. a master device initiates communication by issuing a start (s) condition. a start condition is a high-to-low transition on sda with scl high. a stop (p) condition is a low-to-high transition on sda, while scl is high (figure 10). scl sda data line stable data valid change of data allowed figure 9. i 2 c bit transfer sda scl start condition stop condition figure 10. i 2 c start and stop conditions
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp ______________________________________________________________________________________ 17 a start condition from the master signals the begin- ning of a transmission to the ics. the master termi- nates transmission by issuing a not acknowledge followed by a stop condition (see the acknowledge section for more information). the stop condition frees the bus. to issue a series of commands to the slave, the master can issue repeated start (sr) com- mands instead of a stop command to maintain control of the bus. in general, a repeated start command is functionally equivalent to a regular start command. when a stop condition or incorrect address is detect- ed, the max8649/max8649a internally disconnects scl from the serial interface until the next start con- dition, minimizing digital noise and feedthrough. system configuration a device on the i 2 c bus that generates a message is called a transmitter and a device that receives the mes- sage is a receiver. the device that controls the mes- sage is the master and the devices that are controlled by the master are called slaves. see figure 11. acknowledge the number of data bytes between the start and stop conditions for the transmitter and receiver are unlimited. each 8-bit byte is followed by an acknowl- edge bit. the acknowledge bit is a high-level signal put on sda by the transmitter during which time the master generates an extra acknowledge-related clock pulse. a slave receiver that is addressed must generate an acknowledge after each byte it receives. also, a master receiver must generate an acknowledge after each byte it receives that has been clocked out of the slave transmitter. see figure 12. the device that acknowledges must pull down the data line during the acknowledge clock pulse, so that the data line is stable low during the high period of the acknowledge clock pulse (setup and hold times must also be met). a master receiver must signal an end of data to the transmitter by not generating an acknowl- edge on the last byte that has been clocked out of the slave. in this case, the transmitter must leave sda high to enable the master to generate a stop (p) condition. register reset the i 2 c resisters reset back to their default values when the voltage at either in1 or v dd drops below the corresponding uvlo threshold (see the electrical characteristics table). master transmitter/receiver slave receiver slave transmitter/receiver sda scl figure 11. i 2 cmaster/slave configuration sda output from transmitter sda output from receiver scl from master 1 2 8 9 acknowledge clock pulse for acknowledgement d7 d6 d0 start condition not acknowledge figure 12. i 2 c acknowledge
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp 18 ______________________________________________________________________________________ update of output operation mode if updating the output voltage or operation mode regis- ter for the mode that the ics are currently operating in, the output voltage/operation mode is updated at the same time the ics send the acknowledge for the i 2 c data byte (see figure 13). slave address a bus master initiates communication with a slave device (max8649/max8649a) by issuing a start (s) condition followed by the slave address (the slave address byte consists of 7 address bits (1100 000x for max8649; 1100 010x for max8649a) and a read/write bit (r/ w )). after receiving the proper address, the ics issues an acknowledge by pulling sda low during the ninth clock cycle. the ics provide different i 2 c slave addresses, allowing up to two devices to be used in a system without caus- ing bus collisions. contact the factory for availability. write operations the ics recognize the write byte protocol as defined in the smbus specification and shown in figures 14a and 14b. the write byte protocol allows the i 2 c master device to send 1 byte of data to the slave device. the write byte protocol requires a register pointer address for the sub- sequent write. the ics acknowledge any register pointer even though only a subset of those registers actually exists in the device. the write byte protocol is as follows: 1) the master sends a start command. 2) the master sends the 7-bit slave address followed by a write bit. 3) the addressed slave asserts an acknowledge by pulling sda low. 4) the master sends an 8-bit register pointer. 5) the slave acknowledges the register pointer. 6) the master sends a data byte. 7) the slave acknowledges the data byte. 8) the slave updates with the new data. 9) the master sends a stop (p) condition. in addition to the write-byte protocol, the ics can write to multiple registers as shown in figure 14b. this protocol allows the i 2 c master device to address the slave only once and then send data to a sequential block of regis- ters starting at the specified register pointer. use the following procedure to write to a sequential block of registers: 1) the master sends a start command. 2) the master sends the 7-bit slave address followed by a write bit. 3) the addressed slave asserts an acknowledge by pulling sda low. 4) the master sends the 8-bit register pointer of the first register to write. 5) the slave acknowledges the register pointer. 6) the master sends a data byte. 7) the slave acknowledges the data byte. 8) the slave updates with the new data. 9) steps 6 to 8 are repeated for as many registers in the block, with the register pointer automatically incremented each time. 10) the master sends a stop condition. a: i 2 c start command. b: i 2 c slave address of send out. c: i 2 c register pointer send out. d: data send out. e: issue acknowledge and changes the output voltage according to new i 2 c settings. sda out vid0 vid1 v dd s slave id asr reg ptr asr data a p a b c d e figure 13. update output operation
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp ______________________________________________________________________________________ 19 read operations the method for reading a single register (byte) is shown in figure 15a. to read a single register: 1) the master sends a start command. 2) the master sends the 7-bit slave address followed by a write bit. 3) the addressed slave asserts an acknowledge by pulling sda low. 4) the master sends an 8-bit register pointer. 5) the slave acknowledges the register pointer. 6) the master sends a repeated start (s) condition. 7) the master sends the 7-bit slave address followed by a read bit. 8) the slave asserts an acknowledge by pulling sda low. 9) the slave sends the 8-bit data (contents of the register). 10) the master asserts a not acknowledge by keeping sda high. 11) the master sends a stop (p) condition. in addition, the max8649/max8649a can read a block of multiple sequential registers as shown in figure 15b. use the following procedure to read a sequential block of reg- isters: 1) the master sends a start command. 2) the master sends the 7-bit slave address followed by a write bit. 3) the addressed slave asserts an acknowledge by pulling sda low. 4) the master sends an 8-bit register pointer of the first register in the block. 5) the slave acknowledges the register pointer. 6) the master sends a repeated start condition. 7) the master sends the 7-bit slave address followed by a read bit. 8) the slave asserts an acknowledge by pulling sda low. 9) the slave sends the 8-bit data (contents of the reg- ister). 10) the master asserts an acknowledge by pulling sda low when there is more data to read, or a not acknowledge by keeping sda high when all data has been read. 11) steps 9 and 10 are repeated for as many registers in the block, with the register pointer automatically incremented each time. 12) the master sends a stop condition. 1 s number of bits r/w slave address 7 0 18 register pointer 11 slave to master master to slave legend a) writing to a single register with the write byte protocol 1 s number of bits r/w slave address 7 0 18 register pointer x 1 a 18 data x 1 b) writing to multiple registers ... 8 data x+n-1 1 number of bits ... 8 data x+1 1 a aa a a a 8 data 1 p 1 a 8 data x+n 1 a p figures 14a and 14b. writing to the ics
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp 20 ______________________________________________________________________________________ 1 s number of bits r/w slave address 7 0 18 register pointer 11 17 slave address 1 1 slave to master master to slave legend a) reading a single register 1 s number of bits r/w slave address 7 0 18 register pointer x 1 a 11 7 slave address 1 b) reading multiple registers ... 8 data x+1 1 8 data x+n-1 1 number of bits ... 8 data x 1 r/w a a aa a a sr a 1 8 data 1 p 1 a a 1 1 sr ... 8 data x+n 11 a p r/w figures 15a and 15b. reading from the ics scl sda t r t f t buf start condition stop condition repeated start condition start condition t su_sto t hd_sta t su_sta t hd_dat t su_dat t low t high t hd_sta figure 16. i 2 c timing diagram
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp ______________________________________________________________________________________ 21 pointer register por bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 mode0 0xb4 oper mode sync mode out mode0[5:0] 0x01 mode1 0x1e oper mode sync mode out mode1[5:0] 0x02 mode2 0xb0 oper mode sync mode out mode2[5:0] 0x03 mode3 0x9e oper mode sync mode out mode3[5:0] 0x04 control 0xe0 en_pd vid0_pd vid1_pd 0x05 sync 0x00 sync[1:0] 0x06 ramp 0x01 ramp[2:0] forc e _h y s forc e _os c ram p _d own 0x08 chip_id1 0x20 die type[7:4] die type[3:0] 0x09 chip_id2 0x0e dash[3:0] mask rev[3:0] table 2. i 2 c register map register name mode0 address 0x00h reset value 0xb4h type read/write special features reset upon v dd or in1 uvlo bit name description default value b7 (msb) operation_mode0 dc-dc step-down converter operation mode for mode0 0 = d c - d c conver ter autom ati cal l y chang es b etw een hyster eti c m od e for l i ght load condi ti ons and pwm mod e for m ed ium to heavy l oad cond i tions. 1 = dc-dc converter operates in forced-pwm mode. 1 b6 sync_mode0 disable/enable synchronization to external clock 0 = dc-dc converter ignores the external sync input regardless of operation mode. 1 = d c - d c conver ter synchr oni zes to exter nal s y n c i np ut w hen avai l ab l e. 0 b5 b4 b3 b2 b1 b0 (lsb) out_ mode0 [5:0] output voltage selection for mode0 000000 = 0.75v 000001 = 0.76v 110011 = 1.26v 110100 = 1.27v 110101 = 1.28v 111110 = 1.37v 111111 = 1.38v 110100 table 3. i 2 c register: mode0 this register contains output voltage and operation mode control for mode0, vid0 = gnd, vid1 = gnd.
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp 22 ______________________________________________________________________________________ register name mode1 address 0x01h reset value 0x1eh type read/write special features reset upon v dd or in1 uvlo bit name description default value b7 (msb) operation_mode1 dc-dc step-down converter operation mode for mode1 0 = d c - d c conver ter autom ati cal l y chang es b etw een hyster eti c m od e for l i g ht l oad cond i ti ons and p wm m od e for m ed i um to heavy l oad cond i ti ons. 1 = dc-dc converter operates in forced-pwm mode. 0 b6 sync_mode1 disable/enable synchronization to external clock 0 = dc-dc converter ignores the external sync input regardless of operation mode. 1 = d c - d c conver ter synchr oni zes to exter nal s y n c i np ut w hen avai l ab l e. 0 b5 b4 b3 b2 b1 b0 (lsb) out_mode1[5:0] output voltage selection for mode1 000000 = 0.75v 000001 = 0.76v 011101 = 1.04v 011110 = 1.05v 011111 = 1.06v 111110 = 1.37v 111111 = 1.38v 011110 table 4. i 2 c register: mode1 this register contains output voltage and operation mode control for mode1, vid1 = gnd, vid0 = v dd .
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp ______________________________________________________________________________________ 23 register name mode2 address 0x02h reset value 0xb0h type read/write special features reset upon v dd or in1 uvlo bit name description default value b7 (msb) operation_mode2 dc-dc step-down converter operation mode for mode2 0 = d c - d c conver ter autom ati cal l y chang es b etw een hyster eti c m od e for l i g ht l oad cond i ti ons and p wm m od e for m ed i um to heavy l oad cond i ti ons. 1 = dc-dc converter operates in forced-pwm mode. 1 b6 sync_mode2 disable/enable synchronization to external clock 0 = dc-dc converter ignores the external sync input regardless of operation mode. 1 = d c - d c conver ter synchr oni zes to exter nal s y n c i np ut w hen avai l ab l e. 0 b5 b4 b3 b2 b1 b0 (lsb) out_mode2[5:0] output voltage selection for mode2 000000 = 0.75v 000001 = 0.76v 101110 = 1.21v 101111 = 1.22v 110000 = 1.23v 111110 = 1.37v 111111 = 1.38v 110000 table 5. i 2 c register: mode2 this register contains output voltage and operation mode control for mode2, vid1 = v dd , vid0 = gnd.
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp 24 ______________________________________________________________________________________ register name mode3 address 0x03h reset value 0x9eh type read/write special features reset upon v dd or in1 uvlo bit name description default value b7 (msb) operation_mode3 dc-dc step-down converter operation mode for mode3 0 = d c - d c conver ter autom ati cal l y chang es b etw een hyster eti c m od e for l i g ht l oad cond i ti ons and p wm m od e for m ed i um to heavy l oad cond i ti ons. 1 = dc-dc converter operates in forced-pwm mode. 1 b6 sync_mode3 disable/enable synchronization to external clock 0 = dc-dc converter ignores the external sync input regardless of operation mode. 1 = d c - d c conver ter synchr oni zes to exter nal s y n c i np ut w hen avai l ab l e. 0 b5 b4 b3 b2 b1 b0 (lsb) out_mode3[5:0] output voltage selection for mode3 000000 = 0.75v 000001 = 0.76v 011101 = 1.04v 011110 = 1.05v 011111 = 1.06v 111110 = 1.37v 111111 = 1.38v 011110 table 6. i 2 c register: mode3 this register contains output voltage and operation mode control for mode3, vid1 = v dd , vid0 = v dd .
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp ______________________________________________________________________________________ 25 register name control address 0x04h reset value 0xe0h type read/write special features reset upon v dd , in1 uvlo or en pulled low bit name description default value b7 (msb) en_pd 0 = pulldown on en input is disabled. 1 = pulldown on en input is enabled. 1 b6 vid0_pd 0 = pulldown on vid0 input is disabled. 1 = pulldown on vid0 input is enabled. 1 b5 vid1_pd 0 = pulldown on vid1 input is disabled. 1 = pulldown on vid1 input is enabled. 1 b4 reserved for future use. 0 b3 reserved for future use. 0 b2 reserved for future use. 0 b1 reserved for future use. 0 b0 (lsb) reserved for future use. 0 table 7. i 2 c register: control this register enables or disables pulldown resistors.
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp 26 ______________________________________________________________________________________ register name sync address 0x05h reset value 0x00h type read special features reset upon v dd or in1 uvlo bit name description default value b7 (msb) b6 sync[1:0] sets clock frequency of external clock present on sync input 00 = 26mhz 01 = 13mhz 10 = 19.2mhz 11 = 19.2mhz 00 b5 reserved for future use. 0 b4 reserved for future use. 0 b3 reserved for future use. 0 b2 reserved for future use. 0 b1 reserved for future use. 0 b0 (lsb) reserved for future use. 0 table 8. i 2 c register: sync this register specifies the clock frequency of external clock source.
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp ______________________________________________________________________________________ 27 register name ramp address 0x06h reset value 0x01h type read special features reset upon v dd or in1 uvlo bit name description default value b7 (msb) b6 b5 ramp[2:0] control the ramp timing 000 = 32mv/? 001 = 16mv/? 010 = 8mv/? 011 = 4mv/? 100 = 2mv/? 101 = 1mv/? 110 = 0.5mv/? 111 = 0.25mv/? 000 b4 force_hys only valid when converter is operating in operation_mode 0 0 = automatically change between power-save mode and pwm mode, depending on load current. 1 = converter always operates in power-save mode regardless of load current as long as operation_mode = 0. if operation_mode = 1, this setting is ignored. 0 b3 force_osc force oscillator while running in hysteretic mode 0 = internal oscillator is disabled in power save when operating in hysteretic mode. 1 = internal oscillator is enabled in power save even when operating in hysteretic mode. 0 b2 reserved for future use. 0 b1 ramp_down active ramp-down control for power-save mode 0 = active ramp disabled for power-save mode. 1 = during ramp-down, the error crossing detector is disabled allowing negative current to flow thought the nmos device. 0 b0 (lsb) reserve for future use. 1 table 9. i 2 c register: ramp this register controls of ramp-up/down function.
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp 28 ______________________________________________________________________________________ register name chip_id1 address 0x08h reset value 0x20h type read special features bit name description default value b7 (msb) b6 b5 b4 die_type[7:4] bcd character (2) 0010 b3 b2 b1 b0 (lsb) die_type[3:0] bcd character (0) 0000 table 10. i 2 c register: chip_id1 this register contains the die type number (20). register name chip_id2 address 0x09h reset value 0x0eh type read special features bit name description default value b7 (msb) b6 b5 b4 dash bcd character 0 0000 b3 b2 b1 b0 (lsb) mask_rev bcd character e 1110 table 11. i 2 c register: chip_id2 this register contains the die type dash number and mask revision level.
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp ______________________________________________________________________________________ 29 applications information inductor selection calculate the inductor value (l ideal ) using the follow- ing formula: this sets the peak-to-peak inductor current ripple to 1/4 the maximum output current. the oscillator frequency, f osc , is 3.25mhz, and the duty cycle, d, is: given l ideal , the peak-to-peak inductor ripple current is 0.25 x i out(max) . the peak inductor current is 1.125 x i out(max) . make sure that the saturation current of the inductor exceeds the peak inductor current, and the rated maximum dc inductor current exceeds the maxi- mum output current i out(max) . inductance values small- er than l ideal can be used to reduce inductor size; however, if much smaller values are used, peak inductor current rises and a larger output capacitance may be required to suppress output ripple. larger inductance values than l ideal can be used to obtain higher output current, but typically require a physically larger inductor size. see table 12 for recommended inductors. d v v out in = l vd d if ideal in out max osc = () () 41- manufacturer series inductance (?) dc resistance ( typ) current rating (ma) dimensions l x w x h (mm) ksli-2520ag multilayer 1.0 1.5 2.2 0.075 0.075 0.115 1800 1800 1400 2.5 x 2.0 x 1.0 hitachi metals klsi-2016ag 0.75 1.0 1.5 0.09 0.09 0.13 1500 1500 1100 2.0 x 1.6 x 1.0 fdk mipsa2520d multilayer 0.5 1.3 1.6 2.0 0.11 0.10 0.09 0.06 2000 2000 2000 2000 2.5 x 2.0 x 0.5 ckp3216 multilayer 1.0 1.5 2.2 0.11 0.13 0.14 1100 1000 900 3.2 x 1.6 x 0.9 taiyo yuden nr3015 1.0 1.5 0.03 0.04 2100 1800 3.0 x 3.0 x 1.5 tdk vls3015t 1.0 2.2 0.048 0.070 2000 1400 3.0 x 3.0 x 1.5 toko de2812c 0.56 1.2 1.5 2.0 0.032 0.044 0.050 0.067 2300 1800 1500 1400 3.2 x 3.0 x 1.2 lps3008 0.56 0.80 1.0 1.5 2.2 0.072 0.092 0.125 0.134 1800 1600 1400 1150 3.0 x 3.0 x 0.8 coilcraft lps3010 0.68 1.0 1.5 1.8 2.2 0.070 0.080 0.085 0.120 0.150 2300 1800 1600 1300 1200 3.0 x 3.0 x 1.0 table 12. recommended inductors
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp 30 ______________________________________________________________________________________ input capacitor selection the input capacitor in a step-down dc-dc regulator reduces current peaks drawn from the battery or other input power source and reduces switching noise in the controller. a 10? ceramic capacitor in parallel with a 0.1? ceramic capacitor is recommended for most appli- cations. the impedance of the input capacitor at the switching frequency should be less than that of the input source so that high-frequency switching currents do not pass through the input source. the input capacitor must meet the input ripple-current requirement imposed by the step-down regulator. ceramic capacitors are pre- ferred due to their resilience to power-up surge currents. choose the input capacitor so that the temperature rises due to input ripple current do not exceed approximately +10?. for a step-down dc-dc regulator, the maximum input ripple current is 1/2 of the output. this maximum input ripple current occurs when the step-down regulator operates at 50% duty factor (v in = 2 x v out ). refer to the max8649 evaluation kit data sheet for specific input capacitor recommendations. output capacitor selection the step-down dc-dc regulator output capacitor keeps output ripple small and ensures control-loop stability. a 10? ceramic capacitor in parallel with a 0.1? ceramic capacitor is recommended for most applications. the output capacitor must also have low impedance at the switching frequency. ceramic, poly- mer, and tantalum capacitors are suitable, with ceramic exhibiting the lowest esr and lowest high-frequency impedance. output ripple due to capacitance (neglecting esr) is approximately: additional ripple due to capacitor esr is: refer to the max8649 evaluation kit data sheet for spe- cific output capacitor recommendations. power dissipation the ics have a thermal-shutdown feature that protects the ic from damage when the die temperature exceeds +160?. see the thermal-overload protection section for more information. to prevent thermal overload and allow the maximum load current on each regulator, it is important to ensure that the heat generated by the ics can be dissipated into the pcb. when properly mounted on a multilayer pcb, the junc- tion-to-ambient thermal resistance ( ja ) is typically 76?/w. pcb layout due to fast switching waveforms and high current paths, careful pcb layout is required to achieve optimal perfor- mance. due to fast switching waveforms and high cur- rent paths, careful pcb layout is required to achieve optimal performance. minimize trace lengths between the ics and the inductor, the input capacitor, and the output capacitor; keep these traces short, direct, and wide. the ground connections of c in and c out should be as close together as possible and connected to pgnd. connect agnd and pgnd directly to the ground plane. the max8649 evaluation kit illustrates an exam- ple pcb layout and routing scheme. special care should be taken when routing the remote sense signals. use a wide sns+ trace to minimize parasitic inductance in the sns+ feedback trace. do not use vias on the sns+ trace because they introduce additional inductance. connect sns- to the local agnd plane for the ics. v esr i esr ripple l peak () = () v i fc ripple l peak osc out = () 2 chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 16 wlp 0.5mm pitch w162b2+1 21-0200 refer to application note 1891
max8649/max8649a 1.8a step-down regulator with remote sense in 2mm x 2mm wlp maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 31 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 9/09 initial release 1 2/10 corrected errors in table 1 and figure 2 11, 12 2 9/10 added max8649a to data sheet 1?1 3 2/11 updated the pcb layout section 30 4 6/11 updated remote sense, typical operating circuit , sns+ and sns- input impedance entry, c1 bump description, figure 1, and pcb layout section 1, 5, 10, 11, 30

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